1. Field of the Invention
The present invention relates to a circuit which generates a reference voltage with a prescribed voltage level in a semiconductor device, and particularly to a structure which reduces dependency of the reference voltage upon an external supply voltage and operating temperature.
2. Description of the Background Art
In a semiconductor integrated circuit, a reference voltage at a constant voltage level which has no dependency upon an external supply voltage is frequently required. One of such situations will be described below. For a higher densification and integration of a circuit, semiconductor elements which are the components of the circuit are miniaturized. Since miniaturized semiconductor elements have lower breakdown voltages, a semiconductor integrated circuit comprised of such miniaturized semiconductor elements requires a lower supply voltage (operating supply voltage). In practice, however, there are situations in which an external supply voltage cannot be reduced. For instance, a power supply voltage (operating supply voltage) of a large storage capacity DRAM (Dynamic Random Access Memory) is made lower, considering the breakdown voltage of the elements, the operating speed and power dissipation of DRAM, etc. However, since the components of external devices such as microprocessors and logic LSIs are not miniaturized to the extent of the components of DRAM, the power supply voltage of these external devices cannot be made as low as that of DRAM. Accordingly, when a DRAM, a microprocessor power and the like is utilized to configure a system, a power supply voltage of a high voltage level required by the microprocessor, logic LSI, or the like will be used as the system power source.
When the voltage of the system power supply, that is, the external power supply, is relatively high, a semiconductor device such as DRAM which requires a low operating supply voltage is provided with a circuit which generates an internal supply voltage internally down-converting the external power supply voltage.
FIG. 40 is a schematic diagram showing the entire structure of a semiconductor device such as DRAM which includes an internal voltage down converter circuit as described above. Referring to FIG. 40, a semiconductor device 900 includes an external power supply line 902 which conducts an external supply voltage EXV applied to a power supply terminal 901, another power supply line (hereinafter referred to as a ground line) 904 which conducts the other power supply voltage (hereinafter referred to as a ground voltage) Vss applied to another power supply node (hereinafter referred to as a ground line) 903, and an internal voltage down converter circuit 905 which operates with voltages EXV and Vss on external power supply line 902 and ground line 904 as its both operating power supply voltages and internally down converts external power supply voltage EXV so as to generate an internal power supply voltage VCI on an internal power supply line 906. The structure of this down converter circuit 905, as will be described later, has a function of generating stable internal power supply voltage VCI which is not affected by the variation of external power supply voltage EXV within a predetermined range of external supply voltage EXV.
Semiconductor device 900 further includes an internal power supply utilizing circuit 907 which operates with utilizing voltages VCI and Vss on internal power supply line 906 and ground line 904 as both operating supply voltages, and an external power supply utilizing circuit 908 which operates with external supply voltage EXV on external power supply line 902 and ground voltage Vss on ground line 904 as its both operating supply voltage. This external power supply utilizing circuit 908 is connected to an input/output terminal 909 and serves as an interface with an external device. By utilizing internal voltage down converter circuit 905 to produce internal supply voltage VCI of a prescribed voltage level within semiconductor device 900, the breakdown voltage of elements included in internal power supply utilizing circuit 907 which is the main component of semiconductor device 900 is ensured, and at the same time, improvement in operating speed and reduction in power dissipation by reduction of a signal amplitude are intended.
FIG. 41 is a schematic diagram showing the structure of internal voltage down converter circuit 905 of FIG. 40. Referring to FIG. 41, internal voltage down converter circuit 905 includes a reference voltage generating circuit 910 which generates a reference voltage Vref of a constant voltage level from external supply voltage EXV applied to an external power supply terminal 901, a comparator circuit 912 which compares internal supply voltage VCI on internal power supply line 906 and reference voltage Vref, and a driving element 914 formed of a p channel MOS transistor (insulating gate type field effect transistor) 914 which supplies current from external power supply terminal 901 to internal power supply line 906 in accordance with the output of comparator circuit 912.
Comparator circuit 912 receives external supply voltage VCI at its positive input and reference voltage Vref at its negative input. Comparator circuit 912 is generally constituted of a differential amplifying circuit and differentially amplifies internal supply voltage VCI and reference voltage Vref. The operation of internal voltage down converting circuit 905 will now be outlined hereinbelow.
From reference voltage generating circuit 910, reference voltage Vref of a constant voltage level with no dependency upon external supply voltage EXV is generated. If internal supply voltage VCI on internal power supply line 906 is higher than this reference voltage Vref, the output of comparator circuit 912 will be at H (high) level and driving element 914 is turned off. In this situation, current is not supplied from external power supply terminal 901 to internal power supply line 906.
On the other hand, when internal supply voltage VCI is lower than reference voltage Vref, the output of comparator circuit 912 is at L (low) level and driving element 914 is turned on, so that current is supplied from external power supply terminal 901 to internal power supply line 906, thereby increasing the voltage level of internal supply voltage VCI. Internal supply voltage VCI is maintained at the voltage level of reference voltage Vref by a feedback loop of comparator circuit 912, driving element 914, and internal power supply line 906.
As descried above, since the voltage level of internal supply voltage is decided by reference voltage Vref, it is required that reference voltage Vref has little dependency upon temperature as well as little dependency upon external supply voltage EXV within a prescribed range of external supply voltage EXV when the stability of operation of internal power supply utilizing circuit 907 (see FIG. 25) is taken into consideration.
Such a reference voltage is used in various components other than the internal voltage down converter circuit described above. In an input circuit which inputs an external signal and generates an internal binary signal, a reference voltage is utilized for discrimination between H and L logic levels of this external signal. In a memory device such as a read only memory (ROM) in which data is not read out in a form of a true and complementary read data, a reference voltage is utilized in a circuit for reading and amplifying memory cell data for discrimination between H level and L level of the memory cell data.
In addition, such a reference voltage is also used as a bias voltage of a constant current element included in a differential amplifying circuit. Thus, reference voltage is employed both in a digital integrated circuit and in an analog integrated circuit.
FIG. 42 is a diagram showing a structure of a conventional reference voltage generating circuit shown in, for example, Japanese Patent Laying-Open No. 2-67610. Since the reference voltage may be generated from either an external supply voltage or an internal supply voltage, the power supply voltage is denoted by Vcc in FIG. 42 so that it can cover both external supply voltage and internal supply voltage.
Referring to FIG. 42, the reference voltage generating circuit includes: an enhancement type p channel MOS transistor Q1 connected between a power supply node 1 and an output node 2, and supplying current from power supply node 1 to output node 2 in accordance with voltage on a node 3; an enhancement type p channel MOS transistor Q2 connected between output node 2 and ground line Vss, and having a gate connected to the ground line; an enhancement type p channel MOS transistor Q3 connected between power supply node 1 and node 3, and clamping the voltage of node 3 to a prescribed voltage level; and a resistance element R1 connected between node 3 and ground line Vss and having a resistance value R1.
MOS transistors Q1, Q2, and Q3 have threshold voltages VTP1, VTP2, and VTP3, respectively. MOS transistor Q3 has its gate and drain connected with each other and its back-gate connected to power supply node 1. MOS transistor Q1 has its back-gate connected to power supply node 1, and MOS transistor Q2 has its back-gate connected to output node 2. By setting the potential of source and back-gate of MOS transistor Q2 to an identical value, influence of the back-gate effect is eliminated. Description will now be made of the operation of the circuit.
Conductance coefficients .beta. of MOS transistors Q1, Q2, and Q3 are represented by .beta.1, .beta.2, and .beta.3, respectively. Voltage of node 3 is represented by V3. Assuming that all of MOS transistors Q1 to Q3 are operated in a saturation region, and when voltage of power supply node 1 is expressed Vcc, drain current IDS of MOS transistors Q1 and Q2 can be obtained by: ##EQU1## where V0 is an output voltage of output node 2. If resistance value R1 of resistance element R1 is sufficiently larger than equivalent resistance value of MOS transistor Q3, MOS transistor Q3 functions as a diode and the voltage V3 of node 3 is given by the following equation: EQU V3=Vcc+VTP3 (2)
From equations (1) and (2), voltage V0 which is generated at output node 2 is given by the following equation (3). EQU V0=(.beta.1/.beta.2).sup.1/2 (VTP1-VTP3)-VTP2 (3)
As can be seen from the above equation (3), output voltage V0 is decided by threshold voltages VTP1 to VTP3 of MOS transistors Q1 to Q3 and conductance coefficients .beta.1 and .beta.2 of MOS transistors Q1 and Q2, and has no dependency upon power supply voltage Vcc.
Threshold voltage of an MOS transistor has a dependency upon temperature. In particular, as shown in FIG. 43, a threshold voltage VTN of an n channel MOS transistor is made lower as temperature T is elevated, while a threshold voltage VTP of a p channel MOS transistor is made higher as temperature T is elevated. Referring now to FIG. 43, the axis of abscissas indicates temperature T, and the axis of ordinates indicates voltage value V. When the above equation (3) is considered in terms of this dependency on temperature of the threshold voltages, the difference between the threshold voltages VTP1 and VTP3 is taken in the first term at the right side and thus the temperature dependency of these threshold voltages VTP1 and VTP3 are canceled. Accordingly, this first term at the right side can be deemed a constant having no dependency upon temperature.
However, the second term at the right side is directly influenced by the dependency of threshold voltage VTP2 on temperature. Therefore, output voltage V0 has a dependency upon temperature owing to the dependency of this threshold voltage VTP2 upon temperature. Thus, this output voltage V0 from the reference voltage generating circuit varies according to the change of an operating environmental temperature, and there will be a problem that stable generation of a reference voltage which is always maintained at a constant level cannot be attained.